117 p4c1256 p4c1256 high speed 32k x 8 static cmos ram high speed (equal access and cycle times) 12/15/20/25/35 ns (commercial) 15/20/25/35/45 ns (industrial) 20/25/35/45/55/70 ns (military) low power 880 mw active (commercial) single 5v 10% power supply easy memory expansion using ce ce ce ce ce and oe oe oe oe oe inputs common data i/o functional block diagram pin configurations 1519b
118 p4c1256
119 p4c1256 *v cc = 5.5v. tested with outputs open. f = max. switching inputs are 0v and 3v. ce = v il , oe = v ih . i cc symbol parameter temperature range dynamic operating current* commercial industrial military n/a n/a C15 n/a C12 C20 C25 C35 C45 C55 C70 unit n/a ma ma ma power dissipation characteristics vs. speed n/a n/a n/a n/a 170 160 170 155 165 170 150 145 160 155 150 150 150 155 160 165 ac electrical characteristicsread cycle (v cc = 5v 10%, all temperature ranges) (2) sym. t rc t aa t ac t oh t lz t hz t oe t olz t ohz t pu t pd parameter read cycle time address access time chip enable access time output hold from address change chip enable to output in low z chip disable to output in high z output enable low to low z output enable high to high z chip enable to power up time chip disable to power down time output enable low to data valid min max min max min max min max min max min max min max min max -20 -25 -35 -45 -55 -70 -12 -15 unit 12 2 0 0 12 12 2 5 5 5 12 15 2 2 0 0 15 15 8 7 7 15 20 2 2 0 0 20 20 9 9 9 20 25 3 3 0 0 25 25 11 10 11 20 35 3 3 0 0 35 35 15 15 15 20 45 3 3 0 0 45 45 20 20 20 25 55 3 3 0 0 55 55 25 25 25 30 70 3 3 0 0 70 70 30 30 30 35 ns ns ns ns ns ns ns ns ns ns ns
120 p4c1256
121 p4c1256 notes: 6. ce 1 and we must be low for write cycle. 7. oe is low for this write cycle to show t wz and t ow . 8. if ce 1 goes high simultaneously with we high, the output remains in a high impedance state. -35 ac characteristicswrite cycle (v cc = 5v 10%, all temperature ranges) (2) 9. write cycle time is measured from the last valid address to the first transitioning address. sym. t wc t cw t as t wp t ah t dw t dh parameter write cycle time chip enable time to end of write address set-up time write pulse width address hold time date hold time data valid to end of write min max min max min max min max min max min max min max min max -20 -25 -45 -55 -70 -12 -15 unit 12 0 0 9 0 8 15 11 0 20 15 0 25 0 18 0 35 0 22 0 45 0 25 0 55 0 30 0 70 0 35 0 9 10 0 9 15 0 11 18 20 0 13 22 25 0 15 30 35 0 20 35 40 0 25 40 45 0 30 ns ns ns ns ns ns ns ns t aw address valid to end of write 9 10 15 00 write enable to output in high z t wz 7 8 10 11 15 18 25 30 ns output active from end of write t ow 33335500ns write cycle no. 1 ( we we we we we controlled) (6) address ce t wc data valid high impedance we data in data out data undefined (9) (4) t cw t aw t wp t dw t ah t dh t ow t as t wz (4,7) (7)
122 p4c1256
123 p4c1256 package suffix package suffix p plastic dip, 300 mil wide standard j plastic soj, 300 mil wide standard c sidebrazed dip, 300 mil wide d cerdip, 300 mil wide dw cerdip, 600 mil wide l28 leadless chip carrier, 350 x 550 mils l32 leadless chip carrier, 450 x 550 mils temperature range suffix temperature range suffix c commercial temperature range, 0 c to +70 c. i industrial temperature range, C40?c to +85?c. m military temperature range, C55 c to +125 c. mb mil. temp. with mil-std-883 class b compliance. description description ordering information performance semiconductor's part numbering scheme is as follows: the p4c1256 is also available per smd 5962-88662 1256 p4c ss p t temperature range package code static ram prefix speed (access/cycle time) device number i = ultra-low standby power designator l, if available. ss = speed (access/cycle time in ns). e.g. 25, 35. p = package code, i.e., p, j, c, d, dw, l28, l32. t = temperature range, i.e., c, m. mb.
124 p4c1256
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